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-- Company: 
-- Engineer: 
-- 
-- Create Date: 2022/08/03 16:31:25
-- Design Name: 
-- Module Name: coder8_3 - ART
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

ENTITY coder8_3 IS
  PORT (
    SR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
    SC : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
  );
END coder8_3;

ARCHITECTURE ART OF coder8_3 IS
BEGIN
  PROCESS (SR) IS
  BEGIN
    IF (SR(7) = '0') THEN
      SC <= "000"; --(SR(7)='0')
    ELSIF (SR(6) = '0') THEN
      SC <= "100"; --(SR(7)='1') AND (SR(6)='0')
    ELSIF (SR(5) = '0') THEN
      SC <= "010"; --(SR(7)='1')AND(SR(6)='1')AND(SR(5)='0')
    ELSIF (SR(4) = '0') THEN
      SC <= "110";
    ELSIF (SR(3) = '0') THEN
      SC <= "001";
    ELSIF (SR(2) = '0') THEN
      SC <= "101";
    ELSIF (SR(1) = '0') THEN
      SC <= "011";
    ELSE
      SC <= "111";
    END IF;
  END PROCESS;
END ART;